1. Field of the Invention
The present invention relates to data communication systems and methods, and more particularly relates to a data communication system and method capable of reducing time lag when data is exchanged among various types of buses via networks.
2. Description of the Related Art
FIG. 1 shows an example of the configuration of a conventional network system. In this network system, a digital video cassette recorder (DVCR) 11 is connected to an IEEE1394 (xe2x80x9cInstitute of Electrical and Electronic Engineersxe2x80x9d) serial bus (hereinafter simply referred to as a 1394 serial bus) 12. The 1394 serial bus 12 is connected to an asynchronous transfer mode (ATM) network 15 via a User Network Interface (UNI) 14 from an ATM/1394 repeater 13. The ATM network 15 is connected via a UNI 16 to an ATM/1394 repeater 17. The ATM/1394 repeater 17 is connected via a 1394 serial bus 18 to a DVCR 19.
In the 1394 serial bus 12 (as well as the serial bus 18), data is transmitted as shown in FIG. 2. A source packet as shown by (A) in FIG. 2 contains data from the DVCR 11 and is disassembled into data blocks of 480-byte units as shown by (B) in FIG. 2. These data blocks have an isochronous packet header and a common isochronous packet (CIP) header attached thereto which are transmitted in cycles as isochronous packets with a predetermined timing in a period of 125 xcexcs. A cycle-start packet is transmitted from the cycle master at the start of each cycle. In order to establish synchronization with other devices on the 1394 serial bus 12, every device on the 1394 serial bus 12 has a 32 bit cycle-time register therein. Each device operates, while being synchronized every 125 xcexcs with the value of the cycle-time register thereof by causing the value of the cycle-time register thereof to be reflected by the value of cycle time data of the cycle-start packet (namely, the value of the cycle-time register of the cycle master) which is synchronized with a reference clock frequency of 24.576 MHz (hereinafter referred to as a xe2x80x9cbus reference clockxe2x80x9d) of the cycle master. Accordingly, the ATM/1394 repeater 13 also operates at a place where interface processing between the 1394 serial bus 12 and the ATM/1394 repeater 13 is required, while being synchronized with the value of the cycle-time register.
The 1394 interface unit of the ATM/1394 repeater 13 performs interface processing on the packet data and an ATM interface unit of the ATM/1394 repeater 13 converts the processed packet data into ATM cells. The ATM cells are transmitted via the UNI 14 to the ATM network 15 which operates, while being synchronized with a reference clock frequency of 8 kHz (hereinafter referred to as an ATM reference clock) so as to be synchronized with every device connected thereto. Therefore, the ATM interface unit of the ATM/1394 repeater 13 performs various types of processing synchronized with the ATM reference clock.
The ATM cells are transmitted via the ATM network 15 and the UNI 16 to the ATM/1394 repeater 17. The input ATM cells are reassembled at an ATM interface unit of the ATM/1394 repeater 17. The reassembled data is transmitted to a 1394 interface unit of the ATM/1394 repeater 17 where the data are formed into packets. Then the packet data is transmitted via the 1394 serial bus 18 to the DVCR 19. The ATM interface unit of the ATM/1394 repeater 17 operates, while being synchronized with the ATM reference clock of the ATM network 15 while the 1394 interface unit of the ATM/1394 repeater 17 operates, while being synchronization of the value of the cycle-time register with that of every device connected to the 1394 serial bus 18.
FIGS. 3 is a theoretical timing chart in a case in which, as described above, the data of the DVCR 11 on the 1394 serial bus 12 is transmitted via the ATM network 15 to the DVCR 19 on the 1394 serial bus 18. When the output data of the DVCR 11 is, for example, NTSC (xe2x80x9cNational Television System Committeexe2x80x9d) standard image data, 29.97 Hz frame synchronizing signals are sampled at the 24.576 MHz bus reference clock, for example, at time t1, t4, and t7 (shown by (A) in FIG. 3).
The image data sampled at time t1 is transmitted from the DVCR 11 to the 1394 serial bus 12 by the bus cycle which starts at time t2. At this time, a time stamp is attached to a CIP packet CIP1 (shown by (B) in FIG. 3).
As shown in FIG. 4, an isochronous packet, which is transmitted via the 1394 serial bus 12, includes a 1394 header, a CIPHeader 1, a CIPHeader 2, and data. The CIPHeader 2 contains 16-bit time information SyncTime as the time stamp which is equal to the lower 16 bits of the cycle-time register of any device on the 1394 serial bus 12. The time stamp of the CIP packet CIP1 is obtained by adding the value of an additional delay time TdelayAdd to the value of the cycle-time register at the sampling time (time t1). In other words, the time stamp corresponds to time t3 which is the additional delay time TdelayAdd after time t1. The additional delay time TdelayAdd corresponds to the time for absorbing jitters, such as cycle-timing shift of the 1394 serial bus 12.
When the CIP packet CIP1 is transmitted to the DVR 19 via the 1394 serial bus 18, the DVCR 19 fetches the time stamp contained in the packet (shown by (C) in FIG. 3). Since the time stamp corresponds to time t3, the DVCR 19 generates a frame synchronizing signal for the first frame at time t3. The same processing is sequentially applied to the second frame, the third frame, and so on, one after another.
The timing charts shown in FIG. 3 are theoretical, and an actual timing chart is shown in FIG. 5. That is, the synchronizing signal for the first frame sampled at time t1 is transmitted at time t2 to the 1394 serial bus 12 as the CIP packet CIP1 which includes the time stamp corresponding to time t3 obtained by adding the additional delay time TdelayAdd to the sampling time t1. The CIP packet CIP1 is delayed by a delay time TdelayNet1 which is the total delay time accumulated on each transmission line of the 1394 serial bus 12, the ATM/1394 repeater 13, the UNI 14, the ATM network 15, the UNI 16, ATM/1394 repeater 17, and the 1394 serial bus 18. Finally, the DVCR 19 receives the CIP packet CIP1 at the timing of the bus cycle which starts at time t4. The DVCR 19 fetches the time stamp from the CIP packet CIP1 (shown by (C) in FIG. 5) and generates a synchronizing signal for the first frame at time t6 corresponding to the fetched time stamp (shown by (D) in FIG. 5).
The DVCR 19 connected to the 1394 serial bus 18 on the receiver side times a time ToffsetAddCount1#2 between time t4 and time t6 using the bus reference clock of the 1394 serial bus 18 on the receiver side. Whereas, the DVCR 11 connected to the 1394 serial bus 12 on the sender side sets, as the time stamp of the CIP packet CIP1, time t3 which is a time ToffsetAddCount1#1 after the start time t2 of a bus cycle using the bus reference clock of the 1394 serial bus 12 (shown by (A) in FIG. 5). The time ToffsetAddCount1#1 corresponds to a time difference between time t3 and time t2, in other words, a time difference between time t5 which is a time TdelayNet1 after time t3, and t4 which is the time TdelayNet1 after time t2 (shown by (B) in FIG. 5).
Because the bus reference clock of the 1394 serial bus 12 on the sender side and that of the 1394 serial bus 18 on the receiver side are not synchronized, the cycle of the 1394 serial bus 12 (shown by (B) in FIG. 5) does not exactly correspond to that of the 1394 serial bus 18 (shown by (C) in FIG. 5). Accordingly, a time TsndFrame between time t3 and time t9 as the frame cycle of the 1394 serial bus 12 (shown by (B) in FIG. 5) does not correspond to a time TrevFrame between time t6 and time t13 as the frame cycle of the 1394 serial bus 18 (shown by (D) in FIG. 5).
As a result, there is slight difference between the tone of colors of the image on the DVCR 11 and that of the image on the DVCR 19. Furthermore, there is slight difference between the tone of sound on the DVCR 11 and that on the DVCR 19.
Such a bus cycle difference between both sides brings about an overflow or an underflow in the buffer of the ATM/1394 repeater 17 on the receiver side. Whether the overflow or the underflow occurs is determined by a relative relationship between the bus cycles on both sides. When the bus cycle on the sender side is shorter than that on the receiver side, the overflow occurs; and vice versa. The timing chart in FIG. 5 shows the former case where the longer the accumulated delay time gradually becomes, the more the number of the packets staying in the ATM/1394 repeater 17 increases.
For example, when the size of the buffer in the ATM/1394 repeater 17 is 16 Mbytes and when the relative difference is 30 ppm (the standard deviation of a voltage-controlled crystal oscillator to generate clocks), the time which is required for an overflow to occur in the buffer is computed as follows:
A time Tcip for holding one CIP packet in the buffer of 16 Mbytes:
Tcip=3072/(24.576xc3x9730)=4.17 sec; and
a time Tover required for the overflow to occur in the buffer of 16 Mbytes:
xe2x80x83Tover=Tcipxc3x9716777216/488=143248 sec=39.8 hour.
Therefore, it takes approximately forty hours for an overflow to occur in a buffer of 16 Mbytes.
The time required for an underflow to occur in the buffer is determined by the number of accumulated CIP packets for absorbing jitters and the like. By increasing the number of the accumulated packets, it takes a considerable time for the underflow to occur. However the delay time in the ATM/1394 repeater 17 also increases accordingly. On the contrary, by decreasing the number of accumulated packets, though the delay time is decreased, it does not take much time for the underflow to occur. When, for example, the number of the accumulated CIP packets in the ATM/1394 repeater 17 is 2400 (125xcexcsxc3x972400=300 ms, which is the limit of the delay time for real-time applications) and when the relative difference is 30 ppm, the time required for the underflow to occur is computed as follows.
A time Tcip required for one CIP packet to flow out from the ATM/1394 repeater 17:
Tcip=3072/(24.576xc3x9730)=4.17 sec and;
a time Tunder required for the accumulated CIP packets to underflow:
xe2x80x83Tunder=Tcipxc3x972400=10008 sec=2.78 hour.
Therefore, it takes approximately three hours for the underflow to occur for 2400 accumulated CIP packets.
The present invention is made to solve the foregoing problems. It is an object of the present invention to provide a device capable of restoring information on the receiver side which corresponds to information on the sender side while an occurrence of an overflow or an underflow is prevented.
To this end, according to a first aspect of the invention, there is provided a data communication system for data communication between a bus and a network, the data communication system includes a first interface device for performing interface processing for the bus, a second interface device for performing interface processing for the network, and a generating device for generating a first clock used by the first interface device as a cycle master clock for the bus in synchronization with a second clock used as a reference clock for an ATM network whereby said first clock is synchronized to the second clock by comparing the phase of the clocks and adjusting the first clock. In the data communication system, the bus may be an IEEE1394 serial bus, and the network is an ATM network. Furthermore, the data communication system may includes a control device for controlling the first interface device and the second interface device, and a frequency-dividing device generating an interrupt control signal provided to the control device by performing frequency-division on the second clock.
According to a second aspect of the invention, there is provided a data communication method for data communication between a bus and a network, the data communication method includes a first interfacing step for performing interface processing for the bus, a second interfacing step for performing interface processing for the network, and a generating step for generating a first clock used by the first interfacing step as a cycle master clock for the bus in synchronization with a second clock used as a reference clock for an ATM network whereby said first clock is synchronized to the second clock by comparing the phase of the clocks and adjusting the first clock.